Overview

Computational Lithography and Defect Management

Over the past four decades, Moore’s Law has been the most important benchmark for microelectronics development. It says that the number of transistors on an integrated circuit has increased exponentially, doubling approximately every two years. It can also be interpreted to mean that critical dimensions (CD) of a design must shrink geometrically over time. To achieve small feature sizes, improvements in lithographic resolution were primarily made by moving deeper into ultraviolet spectrum of light. However, the wavelength of the lithography light source has not improved for nearly a decade. This has led to the development of sub-wavelength lithography.

The relationship between optical lithography and minimum feature size is characterized by the Rayleigh equation.

With the wavelength currently at 193nm and the NA at 1.35 for water immersion, resolution enhancement techniques like optical proximity correction (OPC), phase shift masks (PSM) have moved k1 to as low as 0.3 and thus minimum feature sizes have reached 45nm. To achieve 32nm and below, lithographers are turning to Computational Lithography (also referred to as computational scaling).

Computational lithography has become the most viable and economic approach for extending optical lithography for multiple generations. Computational defect management is a necessary complement to computational lithography for filtering photomask defects by using mathematical models to simulate pattern errors on final silicon. The successful commercialization of Computational Lithography and Defect Management by early pioneer, Luminescent, means that for the first time in the history of the semiconductor industry, Moore’s law is being enabled by software innovation rather than advances in hardware-centric lithography technologies.

With device geometries shrinking to sizes well below the wavelength used to image them (e.g., 22nm geometry being imaged with 193nm wavelength), semiconductor companies have turned to computational lithography to bridge the gap in image fidelity. Traditional computational lithography solutions execute a set of rules to iteratively change features on a mask and then model the lithographic system to validate the improvements in pattern fidelity. These techniques require enormous computing resources, and in some cases, cannot create masks with adequate process window.

Luminescent Technologies' approach, Inverse Imaging Technology, addresses the problem from a different perspective. Beginning with the intended pattern on the wafer, we run the inverse of the optical transformation to determine what mask solutions could have created the intended pattern. Out of the possible solutions, we can choose solutions that include the best process window performance or the most manufacturable mask, or a solution that considers both.

Our approach to inverse computing is based on a branch of mathematics called Level Set Methods, invented by Luminescent's co-founder, Stan Osher, a member of the National Academy of Sciences and winner of the SIAM Pioneer Prize. Using the Level Set Method, we can accurately and efficiently model changes in the shapes of the features on the mask. The shapes are "free" to grow in several directions while their impact on lithographic performance is evaluated. These shapes can be both ones that print and ones that do not print, known as Sub-Resolution Assist Features (SRAFs). In traditional OPC, features on a mask must be segmented so changes can be introduced. The OPC program must then rejoin the new shape and then evaluate the lithographic performance. This rule-based segmentation and model-based evaluation is iterative and extremely computing resource intensive. Rule tables tend grow exponentially with each subsequent generation.

Using Inverse Imaging Technology, Luminescent has derived Inverse Lithography Technology and Inverse Inspection Technology to form the fundamental components of the Computational Lithography and Defect Management solution. Using Computational Lithography and Defect Management, the semiconductor industry can rapidly solve for the optimal manufacturable photomask design and ensure that the mask is free of critical defects.

Luminescent Technologies' Computational Lithography and Defect Management product family includes three complementary product platforms with multiple applications serving the needs of lithography development, mask synthesis and mask inspection.

Inverse Lithography Technology (ILT)

To address the needs of the lithography development and OPC teams, Luminescent' created Inverse Lithography Technology (ILT). Products based on ILT are used for both lithography development and mask synthesis. In the early stages of development, litho engineers can explore the mask and illuminator solutions space, as well as, derive the design and SRAF placement rules that the IC designers will use to complete the design. Once the IC design is done and the design is transferred to the OPC group, engineers can use ILT to synthesize a full chip mask layer that has an optimal manufacturing window and adheres to mask manufacturing rules. ILT enables the placement of an optimal set of sub-resolution assist features (SRAFs) while simultaneously generating the rest of the mask. By finding optimal mask patterns, ILT enables superior pattern fidelity, larger process windows, and in the end, improved yields.

Inverse Inspection Technology (IIT)

For the mask inspection teams, Luminescent applies Inverse Imaging Technology to create Inverse Inspection Technology (IIT). Products based on IIT are used to quickly examine and disposition mask defects. With current mask inspection and defect review systems, the image of the defect has low definition and the task of disposition the defect is slow and error prone. Luminescent's computational inspection product begins with an image of a defect on the fabricated mask, and then applies IIT to reconstruct a high definition image of defect at the mask plane. From this mask plane image, we can then forward simulate that mask's performance at the wafer plane. This capability can definitively tell mask inspection engineers if a defect has impact on the final wafer print.

White Paper

For more details on Luminescent's unique technology, read our white paper (pdf).

Patent Position

Luminescent has filed more than 20 patents covering a range of technologies including mathematical methods, lithography techniques, lithography modeling, and CAD/EDA. Our first three patents, 7124394, 7178127, and 7441227 provide broad coverage on the use of level-set methods and iterative optimization in photomask design. Additional patents, both in the U.S. and internationally, are expected to issue soon.