Publications

2011

BACUS 2011 

Efficiency and throughput improvement on defect disposition through automated defect classification [8166-100]

BACUS 2011 

EUV mask absorber and multi-layer defect disposition techniques using computational lithography [8166-08]

BACUS 2011 

EUV multilayer defect compensation (MDC) by absorber pattern modification – From theory to wafer validation [8166-83]

BACUS 2011 

Enabling virtual wafer CD (WCD) using inverse pattern rendering (IPR) of mask CD-SEM images [8166-87]

BACUS 2011 

Exploring the impact of mask making constraints on double patterning design rules [8166-72]

BACUS 2011 

Double patterning for 56 nm pitch test designs using inverse lithography [8166-136]

BACUS 2011 

SMO applied to contact layers at the 32 nm node and below with consideration of MEEF and MRC [8166-19]

SPIE 2011 - Advanced Lithography Symposium 

Hotspot Fixing Using ILT

SPIE 2011 - Advanced Lithography Symposium  

Expanding the Applications of Computational Lithography & Inspection (CLI) in Mask Inspection, Metrology, Review, and Repair [7971-85]

SPIE 2011 - Advanced Lithography Symposium  

Enhancing Fullchip ILT Mask Synthesis Capability for IC Manufacturability

SPIE 2011 - Advanced Lithography Symposium 

Compensation for EUV multilayer defects within arbitrary layouts by absorber pattern modification [7969-48]

 

2010

Lithography Workshop 2010 

Affordable and Process Window Increasing Full Chip Inverse Lithography Technology Masks

BACUS 2010 

Compensation methods using a new model for buried defects in extreme ultraviolet lithography masks

BACUS 2010 

Lithographic Plane Review for sub-32nm Mask Defect Disposition

BACUS 2010 

Computational Lithography & Inspection and its Applications in Mask Inspection, Metrology, Review, and Repair

CSTIC 2010 

From Computational Lithography to Computational Inspection: Inverse Lithography Technology (ILT) and Inverse Inspection Technology (IIT)

SPIE 2010 - Advanced Lithography Symposium 

Computational Inspection Applied to a Mask Inspection System with Advanced Aerial Imaging Capability

SPIE 2010 - Advanced Lithography Symposium 

Optimization from Design Rules, Source and Mask, to Full Chip with a Single Computational Lithography Framework

SPIE 2010 - Advanced Lithography Symposium 

Evaluation of Lithographic Benefits of using ILT Techniques for 22nm-node

SPIE 2010 - Advanced Lithography Symposium 

Source-mask optimization (SMO) from theory to practice

SPIE 2010 - Advanced Lithography Symposium 

Toward a Consistent and Accurate Approach to Modeling Projection Optics

SPIE 2010 - Advanced Lithography Symposium 

Methods for assessing empirical model parameters and calibration pattern measurements

SPIE 2010 - Advanced Lithography Symposium, Lithovision 

Presentation of Source-Mask Co-optimization using Level Set Methods

Litho/Design Co-optimization and Area Scaling for the 22-nm Logic Node

 

2009

Photomask Japan 2009 

Trade-off between inverse lithography mask complexity and lithographic performance

LITHOGRAPHY ASIA 2009 

Source Mask Optimization at Full Chip Scale using Inverse Lithography Technology based on Level Set Methods

BACUS 2009 

Inverse Lithography Technology (ILT) Mask Manufacturability for Full-Chip Device

BACUS 2009 

Mask Pattern Recovery Using Level Set Method and its Application on Defect Auto Disposition based on Simulated Aerial/Wafer Image

BACUS 2009 

Fast and Accurate Computation of Partially Coherent Imaging by Stacked Pupil Shift Operator

BACUS 2009 

Source-Mask co-Optimization (SMO) using Level Set Methods

BACUS 2009 

Patterning of 90nm Node Flash Contact Hole with Assist Feature using KrF

BACUS 2009 

What is a Good Empirical Model?

Photomask Japan 2009 

Mask Defect Auto Disposition based on Aerial Image in Mask Production

SPIE 2009 - Advanced Lithography Symposium 

Exploration of Complex Metal 2D Design Rules Using Inverse Lithography

 

2008

Photomask Japan 2008 

Minimize MEEF in Low k1 Lithography

SPIE 2008 - Advanced Lithography Symposium 

Inverse Lithography as a DFM Tool: Accelerating Design Rule Development with Model-Based Assist Feature Placement, Fast Optical Proximity Correction and Lithographic Hotspot Detection

SPIE 2008 - Advanced Lithography Symposium 

Validation of Inverse Lithography Technology (ILT) and Its Adaptive SRAF at Advanced Technology Nodes

SPIE 2008 - Advanced Lithography Symposium 

Evaluation of Inverse Lithography Technology for 55nm-node memory device

SPIE 2008 - Advanced Lithography Symposium 

Validation and Application of a Mask Model for Inverse Lithography

 

2007

BACUS 2007 

Inverse Lithography Technology (ILT) Keep the balance between SRAF and MRC at 45 and 32-nm

Photomask Japan 2007 

Inverse Lithography Technology (ILT): A Natural Solution for Model-based SRAF at 45nm and 32nm

Photomask Japan 2007 

Application of Sigma7500 pattern generator to X Architecture and 45-nm generation mask making

Semicon China, International Semiconductor Technology Conference (ISTC) 2007 

Inverse Lithography Technology (ILT) and Its Readiness for Production in Advanced Technology Nodes

SPIE 2007 Microlithography Conference 

RAF Placement and Sizing Using Inverse Lithography Technology-

 

Other Key Publications

Fast Inverse Lithography Technology

Inverse Lithography Technology Principles in Practice: Unintuitive Patterns

Inverse Lithography Technology(ILT), What is the Impact to Photomask Industry?

Inverse Lithography Technology (ILT) and its Latest Development -Enabling 45nm Generation with Dry Steppers