Technology

Computational Lithography and Defect Management

Over the past four decades, Moore’s Law has been the most important benchmark for microelectronics development. It says that the number of transistors on an integrated circuit has increased exponentially, doubling approximately every two years. It can also be interpreted to mean that critical dimensions (CD) of a design must shrink geometrically over time. To achieve small feature sizes, improvements in lithographic resolution were primarily made by moving deeper into ultraviolet spectrum of light. However, the wavelength of the lithography light source has not improved for nearly a decade. This has led to the development of sub-wavelength lithography.

The relationship between optical lithography and minimum feature size is characterized by the Rayleigh equation.

With the wavelength currently at 193nm and the NA at 1.35 for water immersion, resolution enhancement techniques like optical proximity correction (OPC), phase shift masks (PSM) have moved k1 to as low as 0.3 and thus minimum feature sizes have reached 45nm. To achieve 32nm and below, lithographers are turning to Computational Lithography (also referred to as computational scaling).

Computational lithography has become the most viable and economic approach for extending optical lithography for multiple generations. Computational defect management is a necessary complement to computational lithography for filtering photomask defects by using mathematical models to simulate pattern errors on final silicon. The successful commercialization of Computational Lithography and Defect Management by early pioneer, Luminescent, means that for the first time in the history of the semiconductor industry, Moore’s law is being enabled by software innovation rather than advances in hardware-centric lithography technologies.